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“The Monotone Circuit Complexity of Boolean Functions,” Combinatorica

Most authors prefer to derive lower bounds on AT2 by partitioning the planar region occupied by chips [59,195,326]. In effect, they employ a physical version of the planar separator theorem. The characterization of VLSI lower bounds in terms of planar circuit complexity introduced by Savage [288] reinforces the connection between memoryless and memory-based computation explored in Chapter 3 but for planar computations by VLSI chips. It also provides an opportunity to introduce the elegant planar separator theorem of Lipton and Tarjan [203]. Lipton and Tarjan [204] developed quadratic lower bounds on the planar circuit size of shifting and matrix multiplication before the connection was established between VLSI complexity and planar circuit size. Improving upon results of [288], McColl [209] and McColl and Paterson [210] show that almost all Boolean functions on n variables require a planar circuit size of Ω(2n) and that this lower bound can be achieved for all functions to within a constant multiplicative factor close to 1. Turan [ ´ 336] has shown that the upper bound of Lemma 12.6.1 is tight by exhibiting a family of functions of linear standard circuit size whose planar circuit size is quadratic. Abelson [1] and Yao [366] studied communication complexity with fixed partitions. Yao [367] and Lipton and Sedgewick [202] made explicit the implicit connection between VLSI communication complexity and the derivation of the AT2 lower bounds. (See also [236], [12], and [194] for a discussion of the conditions under which lower bounds can be derived on the VLSI communication complexity measure.)