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Impact of multiple-etch patterning

A number of startup companies promoting their own disruptive solutions to this problem started to appear, techniques from custom hardware acceleration to radical new algorithms such as Inverse Lithography were touted to resolve the forthcoming bottlenecks. Despite this activity, incumbent OPC suppliers were able to adapt and keep their major customers, with RET and OPC being used together as for previous nodes, but now on more layers and with larger data files, and turn around time concerns were met by new algorithms and improvements in multi-core commodity processors. The term computational lithography was first used by Brion Technology (now a subsidiary of ASML) in 2005[5] to promote their hardware accelerated full chip lithography simulation platform. Since then the term has been used by the industry to describe full chip mask synthesis solutions. As 45 nm goes into full production and EUV lithography introduction is delayed, 32 nm and 22 nm are expected to run on existing 193 nm scanners technology.

Now, not only are throughput and capabilities concerns resurfacing, but also new computational lithography techniques such as source mask optimization (SMO) is seen as a way to squeeze better resolution specific to a given design. Today, all the major mask synthesis vendors have settled on the term “computational lithography” to describe and promote the set of mask synthesis technologies required for 22 nm.

Techniques comprising computational lithography

Computational lithography makes use of a number of numerical simulations to improve the performance (resolution and contrast) of cutting-edge photomasks. The combined techniques include Resolution Enhancement Technology (RET), Optical Proximity Correction (OPC), Source Mask Optimization (SMO), etc.[6] The techniques vary in terms of their technical feasibility and engineering sensible-ness, resulting in the adoption of some and the continual R&D of others.[7]

Resolution enhancement technology

Resolution enhancement technologies, first used in the 90 nanometer generation, using the mathematics of diffraction optics to specify multi-layer phase-shift photomasks that use interference patterns in the photomask that enhance resolution on the printed wafer surface.

Optical proximity correction

Optical proximity correction uses computational methods to counteract the effects of diffraction-related blurring and under-exposure by modifying on-mask geometries with means such as: adjusting linewidths depending on the density of surrounding geometries (a trace surrounded by a large open area will be over-exposed compared with the same trace surrounded by a dense pattern), adding “dog-bone” endcaps to the end of lines to prevent line shortening, correcting for electron beam proximity effects

OPC can be broadly divided into rule-based and model-based.[8] Inverse lithography technology, which treats the OPC as an inverse imaging problem, is also a useful technique because it can provide unintuitive mask pattern